How to Design a 3.2 V / 240 A Planar Transformer for LLC-DCX

1. Freeze the operating point and efficiency boundary

The example targets 3.2–3.6 V at 240 A, with a 480 kHz operating frequency and 500 kHz resonance. Output power is 768 W at 3.2 V and 864 W at 3.6 V. Inputs also include bus range, full- or half-bridge drive, Lm, external Lr, functional insulation, installation height and the thermal boundary of the potted enclosure.

Condition to reconcile first: The source document lists a 38.4 V bus and an 8:1 set ratio that do not yet align. At 3.2 V output, ideal unity gain and negligible synchronous-rectifier drop, a full bridge needs 12:1 and a half bridge needs 6:1. Confirm the bridge, actual transformer voltage and operating gain before fixing the stack-up.

2. Turns ratio and a two-unit ISOP structure

Two 4:1 units have their primaries connected in series and secondaries in parallel to form an 8:1 set. With ideal sharing, each delivers 120 A DC. A sinusoidal-current approximation near resonance gives approximately 133.3 A rms in each secondary and 33.3 A rms in each primary, excluding magnetizing current. Polarity, Lm matching and actual current distribution require verification.

Ideal values at Vo = 3.2 V and unity gain, neglecting rectifier and resonant-network drops. These are conditional ratios.

3. Core window, flux density and interleaved stack-up

The example uses a custom E+I planar core with a geometric cross-section of approximately 56.75 mm². For a one-turn secondary, a 3.2 V ideal symmetric square wave and 480 kHz, Bpk = V / (4fNAc) gives approximately 29.4 mT. Geometric area and typical material losses are screening inputs; the core supplier must confirm Ae, Ve, AL and dimensional tolerances.

Each secondary has eleven parallel 0.20 mm copper foils forming one turn. Ten double-sided 2 oz PCBs form the primary: two turns per board, two boards in series for four turns, and five parallel branches. The foils and PCBs alternate S–P–S–P…–S. The nominal stack is 10 × 0.38 + 11 × 0.30 = 7.10 mm within a nominal 7.8 mm window.

The document's 1-D sinusoidal-field model gives interleaved secondary Fr of approximately 1.39 and primary Fr of 1.04. Two-dimensional end fields, vias, necks, terminals and gap fringing are excluded. These comparisons guide stack-up screening; finished-part AC loss still requires simulation or measurement.

4. Derive the loss budget from the 98.5% target

Allowed loss for both transformers is Ploss = 768 × (1 / 0.985 − 1) ≈ 11.70 W. This efficiency boundary covers only the two transformer ports and excludes Lr, Cr, bridge switches and synchronous rectifiers.

If losses are shared equally at approximately 5.85 W per unit and the allowed hot-spot rise above the cooling boundary is 20 K, each thermal path needs approximately 3.4 K/W or less. Potting, housing, contact interfaces and actual cooling conditions are part of the validation inputs.

5. Lm, Lr, assembly and insulation

The fully interleaved window-leakage model gives approximately 1.7 nH per unit, referred to the primary; end turns and leads still need measurement. The example uses an external Lr. The system's ZVS requirement sets Lm, with pair matching defined by the project.

PCB thickness accumulation can bring the worst-case stack to 7.40 mm. A minimum 7.65 mm window less a 0.30 mm assembly allowance permits only 7.35 mm. A nominal fit therefore does not close the worst-case tolerance. Also verify the five independent series midpoints, polarity, reflow remelting, solder cross-sections and terminal temperature.

The source stack-up is discussed for functional insulation. Basic or reinforced insulation requires a new review of materials, spacing, stack thickness and test requirements.

6. Sample validation and RFQ inputs

• Verify unit and set ratios, polarity, Lm, leakage and current distribution between units.
• Measure finished-port DCR with a four-wire method, including terminals and joints, and correct it to the specified temperature.
• Measure loss and terminal/inner-layer hot spots in the actual DCX at 3.2 V / 240 A and 3.6 V under the customer's thermal boundary.
• Record stack height, window dimensions, total height, reflow process, insulation and reliability checks.

For a design review, provide input/output voltage ranges, bridge type, rated/peak current, frequency, Lm/Lr, efficiency definition, cooling conditions, mounting constraints, insulation requirements and annual volume.

FAQ

Can an 8:1 set be used directly on a 38.4 V bus?

Confirm the bridge, resonant-network gain and actual transformer voltage. Under the document's ideal conditions, 38.4 V to 3.2 V needs 12:1 for a full bridge or 6:1 for a half bridge.

Is 98.5% a measured efficiency?

Here it is a design target for the two transformer ports. Interconnect loss, AC loss and the thermal boundary must be verified on actual samples.

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